Embedded Systems Design

En

Course Description

This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado® Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze™ soft processor are covered in lectures and labs, in addition to general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation. The Xilinx Zynq All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

Release Date

January 2018

Level

Embedded Hardware 3

Training Duration

2 days

Who Should Attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC or MicroBlaze soft processor core using the Embedded Development Kit.

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Skills Gained

After completing this comprehensive training, you will be able to:

  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing a MicroBlaze™ or Cortex™-A9 processor using the Vivado IP integrator and Customization Wizard
  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
  • Create and integrate an IP-based processing system component in the Vivado Design Suite
  • Design and add a custom AXI interface-based peripheral to the embedded processing system
  • Simulate a custom AXI interface-based peripheral using a bus functional model (BFM)

Course Outline

Day 1

  • Embedded UltraFast Design Methodology
  • Overview of Embedded Hardware Development
  • Lab 1: Driving the IP Integrator Tool
  • Overview of Embedded Software Development
  • Lab 2: Driving the SDK Tool
  • AXI: Introduction
  • AXI: Variations
  • Lab 3: AXI: Transactions
  • Introduction to Interrupts
  • Interrupts: Hardware Architecture and Support

Day 2

  • AXI: Connecting AXI IP
  • Lab 4: Using the Create and Import Wizard to Create a New AXI IP
  • Lab 5: AXI: BFM Simulation
  • Lab 6: MicroBlaze Processor Architecture Overview
  • MicroBlaze Processor Block Memory Usage
  • Lab 7: Zynq-7000 All Programmable SoC Architecture Overview

Lab Descriptions

  • Lab 1:Driving the IP Integrator Tool- Introduction to the most commonly performed operations and capabilities of the Vivado IP integrator tool.
  • Lab 2: Driving the IP Integrator Tool- Introduction to the most commonly performed operations and capabilities of the Vivado IP integrator tool.
  • Lab 3: Exploring AXI Transactions Using the AXI Traffic Generator- AXI4 transactions will be explored in this lab with special emphasis on AXI channels, handshaking, and the most useful signal members within the AXI interface.The AXI Traffic Generator (ATG) IP example design will serve as the basis of this lab. Simulation of the design will provide the sample AXI traffic to be studied.
  • Lab 4: Building Custom AXI IP - This lab guides you through the process of creating and adding a custom AXI peripheral to the Vivado IP catalog by using the Create and Package IP Wizard. The focus is on the process of adding an AXI interface onto an existing peripheral—not the actual design of the peripheral logic.
  • Lab 5: BFM Simulation - BFM simulations are used to generate bus stimulus and observe the response to that stimulus. Here you will learn how to run a BFM simulation for a custom peripheral.
  • Lab 6: Exploring the Architecture of the MicroBlaze Processor - Some of the configurable options in the MicroBlaze processor are introduced in this lab. You will learn how to instantiate and configure the MicroBlaze processor and use Designer Assistance to complete a design.
  • Lab 7: Exploring the Architecture of the Zynq-7000 All Programmable SoC - This introduction to the basic process of instantiating and customizing the processor system (PS) of the Zynq-7000 All Programmable SoC family of parts illustrates the process of customizing the PS. While not every aspect of customization is covered, the processes provided here can be extended to all aspects of customization.

Event Schedule

so-logic (top1) (Austria)
  • 29.01. - 30.01.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 19.03. - 20.03.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 29.04. - 30.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 18.06. - 19.06.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 06.08. - 07.08.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 24.09. - 25.09.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 12.11. - 13.11.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-11 14:02to the top