Designing with Verilog

En

Course Description

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Release Date

January 2018

Level

FPGA 1

Training Duration

3 days

Who Should Attend?

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisites

Basic digital design knowledge

Hardware

  • Kintex®-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will be able to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the ISE software design environment
  • Download to the Xilinx demo board

Course Outline

Day 1

  • Hardware Modeling Overview
  • Verilog Language Concepts
  • Modules and Ports
  • Lab 1: Building Hierarchy
  • Introduction to Testbenches
  • Lab 2: Verilog Simulation and RTL Verification

Day 2

  • Verilog Operators and Expressions
  • Data Flow-Level Modeling
  • Lab 3: Memory
  • Verilog Procedural Statements
  • Lab 4: Clock Divider and Address Counter
  • Controlled Operation Statements
  • Lab 5: n-bit Binary Counter and RTL Verification

Day 3

  • Verilog Tasks and Functions
  • Advanced Language Concepts
  • Lab 6: Timing Simulation
  • Finite State Machines
  • Lab 7: Finite State Machines
  • Targeting Xilinx FPGAs
  • Lab 8: Implement and Download
  • Advanced Verilog Testbenches
  • Lab 9: Using Text I/O

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Event Schedule

so-logic (top1) (Austria)
  • 18.02. - 20.02.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 15.04. - 17.04.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 20.05. - 22.05.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 15.07. - 17.07.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 26.08. - 28.08.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 14.10. - 16.10.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 02.12. - 04.12.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-18 10:36to the top