Designing with VHDL

En

Course Description

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Release Date

January 2018

Training Duration

3 days

Who Should Attend?

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.

Prerequisites

Basic digital design knowledge

Hardware

  • Architecture: N/A*
  • Demo board: Spartan demo board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this training, you will be able to:

  • Implement the VHDL portion of coding for synthesis
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
    • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the ISE software environment

Course Outline

Day 1

  • The "Shape" of VHDL
  • Lab 1: Using the Tools
  • Documentation in VHDL
  • Data Types
  • Concurrent Operations
  • Lab 2: Using Concurrent Statements
  • Processes and Variables
  • Lab 3: Designing a Simple Process

Day 2

  • Introduction to Testbenches
  • ISim Simulation Tool Basics
  • Lab 4: Simulating a Simple Design
  • Creating Memory
  • Lab 5: Building a Dual-Port Memory
  • Finite State Machines
  • Lab 6: Building a Moore Finite State Machine
  • Targeting Xilinx FPGAs
  • Lab 7: Xilinx Tool Flow

Day 3

  • Loops and Conditional Elaboration
  • Lab 8: Using Loops
  • Attributes
  • Functions and Procedures
  • Packages and Libraries
  • Lab 9: Building Your Own Package
  • Interacting with the Simulation
  • Writing a Good Testbench
  • Lab 10: Building a Meaningful Testbench

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.

Event Schedule

so-logic (top1) (Austria)
  • 18.02. - 20.02.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 15.04. - 17.04.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 20.05. - 22.05.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 15.07. - 17.07.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 26.08. - 28.08.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 14.10. - 16.10.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart
  • 02.12. - 04.12.2019 09:00-17:00 — € 2,250.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-11 14:09to the top