Designing FPGAs Using the Vivado Design Suite 2

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Course Description

This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Release Date

January 2018

Level

FPGA 2

Training Duration

2 days

Who Should Attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

Optional Videos

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Build resets into your system for optimum reliability and design speed
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Describe the HLx design flow that increases productivity
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Day 1

  • UltraFast Design Methodology Introduction {Lecture}
  • Scripting in Vivado Design Suite Project Mode {Lecture, Lab}
  • Clocking Resources {Lecture, Lab}
  • Synchronous Design Techniques {Lecture}
  • Register Duplication {Lecture}
  • Resets {Lecture, Lab}
  • I/O Logic Resources {Lecture}
  • Timing Summary Report {Lecture, Demo}
  • Introduction to Timing Exceptions {Lecture, Lab, Demo}
  • Generated Clocks {Lecture, Demo}
  • Clock Group Constraints {Lecture, Demo}

Day 2

  • Creating and Packaging Custom IP {Lecture, Lab}
  • Using an IP Container {Lecture, Demo}
  • Designing with IP Integrator {Lecture, Lab, Demo}
  • Introduction to the HLx Design Flow {Lecture, Lab, Demo}
  • Configuration Process {Lecture}
  • Sampling and Capturing Data in Multiple Clock Domains {Lecture, Lab}
  • Design Analysis Using Tcl Commands {Lecture, Lab, Demo}
  • Power Analysis and Optimization Using the Vivado Design Suite {Lecture, Lab}

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction – Overview of the methodology guidelines covered in this course.
  • Scripting in Vivado Design Suite Project Mode – Explains how to write Tcl commands in the project-based flow for a design.
  • Clocking Resources – Describes various clock resources, clocking layout, and routing in a design.
  • Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.
  • Register Duplication – Use register duplication to reduce high fanout nets in a design.
  • Resets – Investigates the impact of using asynchronous resets in a design.
  • I/O Logic Resources – Overview of I/O resources and the IOB property for timing closure.
  • Timing Summary Report – Use the post-implementation timing summary report to sign-off criteria for timing closure.
  • Introduction to Timing Exceptions – Introduces timing exception constraints and applying them to fine tune design timing.
  • Generated Clocks – Use the report clock networks report to determine if there are any generated clocks in a design.
  • Clock Group Constraints – Apply clock group constraints for asynchronous clock domains.

Day 2

  • Creating and Packaging Custom IP – Create your own IP and package and include it in the Vivado IP catalog.
  • Using an IP Container – Use a core container file as a single file representation for an IP.
  • Designing with IP Integrator – Use the Vivado IP integrator to create the uart_led subsystem.
  • Introduction to the HLx Design Flow – Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
  • Configuration Process – Understand the FPGA configuration process, such as device power up, CRC check, etc.
  • Sampling and Capturing Data in Multiple Clock Domains – Overview of debugging a design with multiple clock domains that require multiple ILAs.
  • Design Analysis Using Tcl Commands – Analyze a design using Tcl commands.
  • Power Analysis and Optimization Using the Vivado Design Suite – Use report power commands to estimate power consumption.

Event Schedule

so-logic (top1) (Austria)
  • 16.01. - 17.01.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 06.03. - 07.03.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 25.04. - 26.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 05.06. - 06.06.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 31.07. - 01.08.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 11.09. - 12.09.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 30.10. - 31.10.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-18 10:46to the top