Zynq UltraScale+ MPSoC for the Hardware Designer

This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.The emphasis is on:Identifying the key ele...

Course Description

This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective. It covers the APU, RPU, power domains, PS–PL connectivity, and hardware emulation using QEMU.

The emphasis of this course is on:

• Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• Reviewing the various power domains and their control structure
• Illustrating the processing system (PS) and programmable logic (PL) connectivity
• Utilizing QEMU to emulate hardware behavior

Training Duration

22 hours

Additional Information

• Number of Chapters: 12
• Number of Labs: 7
• Number of Demos: 1
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• Application Processing Unit

Chapter 2

• Real-Time Processing Unit

Chapter 3

• QEMU

Chapter 4

• Booting – HW

Chapter 5

• First Stage Boot Loader – HW

Chapter 6

• Video

Chapter 7

• System Protection

Chapter 8

• Clocks and Resets

Chapter 9

• AXI

Chapter 10

• Power Management and PMU

Chapter 11

• Debugging Using Cross-Triggering

Chapter 12

• Zynq UltraScale+ MPSoC for the Hardware Designer Full Course Quiz