Designing FPGAs Using the Vivado Design Suite 1

This course offers introductory training on the AMD Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design. The course provides experience with: Creating a Vivado Design Suite project with source files Simulating a design Performing pin assignments Applying basic timing constraints Synthesizing and implementing Debugging a design Generating and downloading a bitstream onto a demo board

Course Description

This course introduces the FPGA design flow using the AMD Vivado™ Design Suite. It provides experience with creating projects, adding source files, simulating designs, performing pin assignments, applying basic timing constraints, synthesizing and implementing designs, debugging, and generating and downloading bitstreams onto a demo board.

The emphasis of this course is on:

• Creating a Vivado Design Suite project with source files
• Simulating a design
• Performing pin assignments
• Applying basic timing constraints
• Synthesizing and implementing a design
• Debugging a design
• Generating and downloading a bitstream onto a demo board

Training Duration

20 hours

Additional Information

• Number of Chapters: 29
• Number of Labs: 10
• Number of Demos: 6
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• Introduction to FPGAs

Chapter 2

• AMD FPGA and Adaptive SoC Portfolio

Chapter 3

• Introduction to the AMD Vivado™ Design Suite

Chapter 4

• Introduction to the Tcl Environment

Chapter 5

• AMD Vivado™ Design Suite Project-Based Mode

Chapter 6

• AMD Vivado™ Design Suite Non-Project Based Mode

Chapter 7

• UltraFast Design Methodology – Board and Device Planning

Chapter 8

• RTL Development

Chapter 9

• Behavioral Simulation

Chapter 10

• AMD Vivado™ IP Flow

Chapter 11

• AMD Vivado™ Synthesis and Implementation and Bitstream Generation

Chapter 12

• Basic Design Analysis in the Vivado IDE

Chapter 13

• Vivado Design Rule Checks

Chapter 14

• Introduction to AMD Vivado™ Reports

Chapter 15

• Introduction to Clock Constraints

Chapter 16

• Generated Clocks

Chapter 17

• I/O Constraints and Virtual Clocks

Chapter 18

• Timing Constraints Wizard

Chapter 19

• Static Timing Analysis (STA)

Chapter 20

• SetUp and Hold Violation Analysis

Chapter 21

• AMD Vivado™ Design Suite IO Pin Planning

Chapter 22

• Power Estimation Using XPE

Chapter 23

• Understanding Design Powers – F1

Chapter 24

• AMD Versal™ Adaptive SoC Power Design Manager_F1

Chapter 25

• Introduction to FPGA Configuration

Chapter 26

• Introduction to the AMD Vivado™ Logic Analyzer

Chapter 27

• Introduction to Triggering

Chapter 28

• Debug Cores

Chapter 29

• Designing FPGAs Using the Vivado Design Suite 1 Full Course Quiz