Designing FPGAs Using the Vivado Design Suite 2

Learn how to build a more effective FPGA design: The focus is on: Using synchronous design techniques Utilizing the Vivado™ IP integrator to create a sub-system Performing power analysis and optimization to improve the power efficiency of a design Reviewing and analyzing timing reports for a design

Course Description

This course teaches how to build a more effective FPGA design. It focuses on synchronous design techniques, creating sub-systems using the Vivado™ IP integrator, performing power analysis and optimization, and reviewing and analyzing timing reports. It builds on the concepts introduced in the Designing FPGAs Using the Vivado Design Suite 1 course.

The emphasis of this course is on:

• Using synchronous design techniques
• Utilizing the Vivado™ IP integrator to create a sub-system
• Performing power analysis and optimization to improve design power efficiency
• Reviewing and analyzing timing reports for a design

Training Duration

21 hours

Additional Information

• Number of Chapters: 21
• Number of Labs: 9
• Number of Demos: 6
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• UltraFast Design Methodology – Design Creation

Chapter 2

• Synchronous Design Techniques

Chapter 3

• Resets

Chapter 4

• Register Duplication

Chapter 5

• Using Tcl Commands in the AMD Vivado™ Design Suite Project Flow

Chapter 6

• Scripting in AMD Vivado™ Design Suite Non-Project Mode

Chapter 7

• AMD UltraScale Architecture Clocking Resources

Chapter 8

• UltraScale Architecture I/O Resources – F2

Chapter 9

• Getting Started with Vivado IP Integrator

Chapter 10

• Designing IP Subsystems Using Vivado IP Integrator: Introduction

Chapter 11

• Block Design Containers in the AMD Vivado™ IP Integrator – Introduction

Chapter 12

• Creating and Packaging Custom IP

Chapter 13

• Using an IP Container

Chapter 14

• Report Clock Networks

Chapter 15

• Timing Summary Report

Chapter 16

• Clock Group Constraints

Chapter 17

• Introduction to Timing Exceptions

Chapter 18

• Power Analysis and Optimization Using the AMD Vivado™ Design Suite

Chapter 19

• Configuration Process

Chapter 20

• HDL Instantiation Debug Probing Flow

Chapter 21

• Designing FPGAs Using the Vivado Design Suite 2 Full Course Quiz