Designing FPGAs Using the Vivado Design Suite 3

Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL coding techniques that help with design timing closure Illustrating the advanced capabilities of the Vivado™ logic analyzer to debug a design

Course Description

This course teaches how to effectively employ timing closure techniques. It demonstrates baselining, pipelining, and synchronization circuits, shows optimum HDL coding techniques that support timing closure, and illustrates advanced capabilities of the Vivado™ logic analyzer for design debugging. It builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.

The emphasis of this course is on:

• Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
• Showing optimum HDL coding techniques that help with design timing closure
• Illustrating advanced capabilities of the Vivado™ logic analyzer to debug a design

Training Duration

21 hours

Additional Information

• Number of Chapters: 23
• Number of Labs: 12
• Number of Demos: 6
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• UltraFast Design Methodology – Implementation

Chapter 2

• Timing Simulation

Chapter 3

• Baselining

Chapter 4

• Pipelining

Chapter 5

• Inference

Chapter 6

• I/O Timing Scenarios

Chapter 7

• System-Synchronous I/O Timing

Chapter 8

• Source-Synchronous I/O Timing

Chapter 9

• Timing Constraints Priority

Chapter 10

• Report Clock Interaction

Chapter 11

• Report Datasheet

Chapter 12

• QoR Reports Overview

Chapter 13

• Sampling and Capturing Data in Multiple Clock Domains

Chapter 14

• Clock Domain Crossing and Synchronization Circuits

Chapter 15

• Revision Control Systems in the Vivado Design Suite

Chapter 16

• Dynamic Power Estimation Using Vivado Report Power

Chapter 17

• Configuration Modes

Chapter 18

• Netlist Insertion Debug Probing Flow

Chapter 19

• JTAG to AXI Master Core

Chapter 20

• Debug Flow in an IP Integrator Block Design

Chapter 21

• Remote Debugging Using the Vivado Logic Analyzer

Chapter 22

• Design Analysis Using Tcl Commands

Chapter 23

• Designing FPGAs Using the Vivado Design Suite 3 Full Course Quiz