Designing with Versal AI Edge Series Gen 2: AIE-ML v2 Architecture and Design Flow

This course outlines the architecture of AMD Versal™ AI Engine ML v2 (AIE-ML v2), a part of AMD Versal AI Edge Series Gen 2 devices, and explores the features and key architectural enhancements.

Course Description

This course outlines the architecture of the AMD Versal™ AI Engine ML v2 (AIE‑ML v2), a part of the AMD Versal AI Edge Series Gen 2 devices, and explores the features and key architectural enhancements introduced with this iteration of AI Engines.

This course provides an overview of both native and supported data types and highlights how to program the AI Engine and migrate older AI Engine designs. Enhancements included in AIE‑ML v2, the usage of DSP libraries, compute capabilities, and performance analysis are also demonstrated.

The emphasis of this course is on:

• Providing an overview of the new AI Engine (AIE‑ML v2) architecture
• Describing the system design planning and application partitioning methodology
• Describing the AMD Vitis™ and AI Engine tool flow
• Providing an overview of the native and supported data types for functional implementation in AIE‑ML v2
• Illustrating the programming model and the usage of memory tiles (shared buffers) for AIE‑ML v2
• Utilizing the Vitis DSP library for AI Engines in implementing matrix multiplication with multiple tiles
• Analyzing reports using the Vitis Analysis view and reviewing throughput and performance of different AI Engine architectures

Training Duration

13 hours

Additional Information

• Number of Chapters: 9
• Number of Labs: 4
• Number of Demos: 0
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• AMD Versal Adaptive SoC: Architecture Overview

Chapter 2

• Introduction to the AIE‑ML v2 Architecture

Chapter 3

• Versal AI Edge Series Gen 2: Application Partitioning

Chapter 4

• Versal AI Edge Series Gen 2: AIE‑ML v2 Tool Flow

Chapter 5

• Supported Data Types for AIE‑ML v2

Chapter 6

• The Programming Model and AIE‑ML v2 Memory Tiles

Chapter 7

• Overview of the AI Engine DSP Library with AIE‑ML v2

Chapter 8

• Analyzing the AI Engine Design Reports and Performance

Chapter 9

• Designing with Versal AI Edge Series Gen 2 AIE‑ML v2 Architecture and Design Flow: Architecture Quiz