Admin >>
Customer login
  • so-logic
  • sozius
  • Aktivitäten
  • Wissensbasis
  • Trainings
  • IPs
  • Kunden
  • Sitemap

Trainings

  • soopendays 2012
  • Suche
  • Kursplan
  • In-house Training
  • Create attendant account
  • Doulos
  • Mathworks
  • National Instruments
  • So-logic
  • Xilinx
    • C++ for Adaptive SOC
    • Architecture
    • Connectivity
    • DSP
    • Embedded
    • HDL
    • Tools
      • Vitis Design flow
      • Vivado Design Suite for ISE Project Navigator Users
      • Designing FPGAs Using the Vivado Design Suite 1
      • Designing FPGAs Using the Vivado Design Suite 2
      • Designing FPGAs Using the Vivado Design Suite 3
      • Designing FPGAs Using the Vivado Design Suite 4
      • UltraFast Design Methodology
      • Vivad Design Suite for ISE Software Project Navigator Users
      • Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
      • Partial Reconfiguration Tools & Techniques
    • Versal Live Online Workshop Compendium Complete
    • Vision KRIA SOM
  • Zahlungsbedingungen
  • Einkaufswagen
  • Anleitung

Tools

Courses

  • Vitis Design flow
  • Vivado Design Suite for ISE Project Navigator Users
  • Designing FPGAs Using the Vivado Design Suite 1
  • Designing FPGAs Using the Vivado Design Suite 2
  • Designing FPGAs Using the Vivado Design Suite 3
  • Designing FPGAs Using the Vivado Design Suite 4
  • UltraFast Design Methodology
  • Vivad Design Suite for ISE Software Project Navigator Users
  • Vivado Advanced XDC and Static Timing Analysis for ISE Software Users
  • Partial Reconfiguration Tools & Techniques
Updated at: to the top
 
Questions or problems? support@so-logic.netWKO Impressum, Privacy and Policy