Training schedules 2024-06-24 - 2025-06-24

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Event period Training Partner Location Price
26.06. - 27.06.2024 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
28.06. - 28.06.2024 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 800.00 Add to cart
01.07. - 05.07.2024 09:00-17:00 Design Compendium Verfication with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
03.07. - 05.07.2024 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
07.07. - 11.07.2024 09:00-17:00 Design Compendium with SystemC for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
08.07. - 08.07.2024 09:00-17:00 Migrating to the Vitis Embedded Software Development IDE Workshop Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
08.07. - 12.07.2024 09:00-17:00 Design Compendium with Verilog for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
08.07. - 08.07.2024 09:00-17:00 AMD Versal Compendium 2 : High Speed Communication so-logic so-logic (top1) (Austria) € 0.00 Add to cart
10.07. - 12.07.2024 09:00-17:00 High-Level Synthesis with Vitis HLS Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
15.07. - 16.07.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
17.07. - 18.07.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
21.07. - 22.07.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
22.07. - 25.07.2024 09:00-17:00 Design Compendium with High Level Synthesis for AMX Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
23.07. - 24.07.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
28.07. - 30.07.2024 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
29.07. - 02.08.2024 09:00-17:00 Design Compendium with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
31.07. - 01.08.2024 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
04.08. - 06.08.2024 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
05.08. - 09.08.2024 09:00-17:00 Design Compendium Embedded System for AMD XIlinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
07.08. - 08.08.2024 09:00-17:00 Designing with SystemVerilog Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
11.08. - 12.08.2024 09:00-17:00 Verification with SystemVerilog Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
12.08. - 16.08.2024 09:00-17:00 Design Compendium Yocto for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
13.08. - 14.08.2024 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
02.09. - 03.09.2024 09:00-17:00 Designing with Versal AI Engine 1 - Architecture and Design Flow Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
04.09. - 06.09.2024 09:00-17:00 Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
09.09. - 13.09.2024 09:00-17:00 Design Compendium with Verilog for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
09.09. - 11.09.2024 09:00-17:00 Designing with Versal AI Engine 3: Kernel Programming and Optimization Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
09.09. - 09.09.2024 09:00-17:00 AMD Versal Compendium 3 : AI Engine so-logic so-logic (top1) (Austria) € 0.00 Add to cart
09.09. - 13.09.2024 09:00-17:00 Design Compendium Verfication with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
12.09. - 13.09.2024 09:00-17:00 Designing with the Versal ACAP: PCI Express Systems Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
16.09. - 20.09.2024 09:00-17:00 Design Compendium with SystemC for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
16.09. - 19.09.2024 09:00-17:00 Designing with the Versal ACAP: Architecture and Methodology Xilinx so-logic (top1) (Austria) € 3,200.00 Add to cart
20.09. - 20.09.2024 09:00-17:00 Designing with the Versal ACAP: Network on Chip Xilinx so-logic (top1) (Austria) € 800.00 Add to cart
22.09. - 23.09.2024 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
23.09. - 27.09.2024 09:00-17:00 Design Compendium with High Level Synthesis for AMX Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
24.09. - 25.09.2024 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
26.09. - 26.09.2024 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 800.00 Add to cart
30.09. - 04.10.2024 09:00-17:00 Design Compendium with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
01.10. - 03.10.2024 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
04.10. - 08.10.2024 09:00-17:00 Design Compendium Embedded System for AMD XIlinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
06.10. - 07.10.2024 09:00-17:00 Migrating to the Vitis Embedded Software Development IDE Workshop Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
08.10. - 10.10.2024 09:00-17:00 High-Level Synthesis with Vitis HLS Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
13.10. - 14.10.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
14.10. - 18.10.2024 09:00-17:00 Design Compendium Yocto for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
15.10. - 16.10.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
20.10. - 21.10.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
22.10. - 23.10.2024 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
27.10. - 29.10.2024 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
30.10. - 31.10.2024 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
03.11. - 05.11.2024 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
04.11. - 08.11.2024 09:00-17:00 Design Compendium Verfication with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
06.11. - 07.11.2024 09:00-17:00 Designing with SystemVerilog Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
10.11. - 11.11.2024 09:00-17:00 Verification with SystemVerilog Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
11.11. - 15.11.2024 09:00-17:00 Design Compendium with Verilog for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
12.11. - 13.11.2024 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
18.11. - 22.11.2024 09:00-17:00 Design Compendium with SystemC for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
25.11. - 29.11.2024 09:00-17:00 Design Compendium with High Level Synthesis for AMX Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
02.12. - 06.12.2024 09:00-17:00 Design Compendium with VHDL for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
02.12. - 03.12.2024 09:00-17:00 Designing with Versal AI Engine 1 - Architecture and Design Flow Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
04.12. - 06.12.2024 09:00-17:00 Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
09.12. - 11.12.2024 09:00-17:00 Designing with Versal AI Engine 3: Kernel Programming and Optimization Xilinx so-logic (top1) (Austria) € 2,400.00 Add to cart
09.12. - 13.12.2024 09:00-17:00 Design Compendium Embedded System for AMD XIlinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
12.12. - 16.12.2024 09:00-17:00 Design Compendium Yocto for AMD Xilinx devices so-logic so-logic (top1) (Austria) € 4,000.00 Add to cart
12.12. - 13.12.2024 09:00-17:00 Designing with the Versal ACAP: PCI Express Systems Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
16.12. - 19.12.2024 09:00-17:00 Designing with the Versal ACAP: Architecture and Methodology Xilinx so-logic (top1) (Austria) € 3,200.00 Add to cart
20.12. - 20.12.2024 09:00-17:00 Designing with the Versal ACAP: Network on Chip Xilinx so-logic (top1) (Austria) € 800.00 Add to cart