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06.10. - 07.10.2024 09:00-17:00
|
Migrating to the Vitis Embedded Software Development IDE Workshop
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
08.10. - 10.10.2024 09:00-17:00
|
High-Level Synthesis with Vitis HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
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|
|
13.10. - 14.10.2024 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
14.10. - 18.10.2024 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
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|
|
15.10. - 16.10.2024 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
20.10. - 21.10.2024 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
22.10. - 23.10.2024 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
27.10. - 29.10.2024 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
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|
|
30.10. - 31.10.2024 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
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|
|
03.11. - 05.11.2024 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
04.11. - 08.11.2024 09:00-17:00
|
Design Compendium Verfication with VHDL for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
06.11. - 07.11.2024 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
10.11. - 11.11.2024 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
11.11. - 11.11.2024 09:00-17:00
|
AMD Versal Compendium 3 : AI Engine
|
so-logic
|
so-logic (top1) (Austria)
|
€ 0.00
|
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|
|
11.11. - 15.11.2024 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
12.11. - 13.11.2024 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
18.11. - 22.11.2024 09:00-17:00
|
Design Compendium with SystemC for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
25.11. - 29.11.2024 09:00-17:00
|
Design Compendium with High Level Synthesis for AMX Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
02.12. - 06.12.2024 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
02.12. - 03.12.2024 09:00-17:00
|
Designing with Versal AI Engine 1 - Architecture and Design Flow
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
04.12. - 06.12.2024 09:00-17:00
|
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
09.12. - 11.12.2024 09:00-17:00
|
Designing with Versal AI Engine 3: Kernel Programming and Optimization
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
09.12. - 13.12.2024 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
12.12. - 16.12.2024 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
so-logic (top1) (Austria)
|
€ 4,000.00
|
Add to cart
|
|
12.12. - 13.12.2024 09:00-17:00
|
Designing with the Versal ACAP: PCI Express Systems
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
16.12. - 19.12.2024 09:00-17:00
|
Designing with the Versal ACAP: Architecture and Methodology
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 3,200.00
|
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|
|
20.12. - 20.12.2024 09:00-17:00
|
Designing with the Versal ACAP: Network on Chip
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
