|
16.12. - 17.12.2027 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
13.12. - 14.12.2027 09:00-17:00
|
Designing with Versal AI Engine: DSP Applications
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.12. - 07.12.2027 09:00-17:00
|
Designing with Versal AI Edge Series Gen 2: AIE-ML v2 Architecture and Design Flow
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.11. - 25.11.2027 09:00-17:00
|
Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
18.11. - 19.11.2027 09:00-17:00
|
Migration from Intel to AMD x86 Embedded Solutions -1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.11. - 17.11.2027 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.11. - 12.11.2027 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.11. - 09.11.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.10. - 29.10.2027 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
27.10. - 28.10.2027 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
25.10. - 26.10.2027 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
15.10. - 15.10.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
13.10. - 14.10.2027 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.10. - 15.10.2027 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
23.09. - 24.09.2027 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
20.09. - 24.09.2027 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
20.09. - 22.09.2027 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
11.09. - 12.09.2027 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.09. - 09.09.2027 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.09. - 10.09.2027 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
06.09. - 07.09.2027 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.08. - 18.08.2027 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
16.08. - 17.08.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.08. - 06.08.2027 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
04.08. - 05.08.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.08. - 06.08.2027 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
02.08. - 03.08.2027 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.07. - 16.07.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.07. - 13.07.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.07. - 09.07.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
05.07. - 09.07.2027 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
05.07. - 06.07.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Quick Start
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.06. - 15.06.2027 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.06. - 10.06.2027 09:00-17:00
|
Designing with Versal AI Engine: DSP Applications
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.06. - 08.06.2027 09:00-17:00
|
Designing with Versal AI Edge Series Gen 2: AIE-ML v2 Architecture and Design Flow
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.05. - 31.05.2027 09:00-17:00
|
Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
24.05. - 27.05.2027 09:00-17:00
|
Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
19.05. - 20.05.2027 09:00-17:00
|
Migration from Intel to AMD x86 Embedded Solutions -1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.05. - 13.05.2027 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
10.05. - 11.05.2027 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
03.05. - 04.05.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.04. - 29.04.2027 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
26.04. - 27.04.2027 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.04. - 16.04.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
14.04. - 15.04.2027 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.04. - 13.04.2027 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.04. - 16.04.2027 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
18.03. - 19.03.2027 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.03. - 19.03.2027 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
15.03. - 17.03.2027 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
03.03. - 04.03.2027 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.03. - 02.03.2027 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.03. - 05.03.2027 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
15.02. - 16.02.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.02. - 17.02.2027 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
05.02. - 05.02.2027 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
03.02. - 04.02.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.02. - 02.02.2027 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.01. - 15.01.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.01. - 12.01.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.01. - 08.01.2027 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.01. - 05.01.2027 09:00-17:00
|
Designing with the Versal Adaptive SoC: Quick Start
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.01. - 08.01.2027 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
23.12. - 23.12.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
21.12. - 22.12.2026 09:00-17:00
|
Developing AI Inference Solutions with the Vitis AI Platform
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.12. - 17.12.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.12. - 15.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.12. - 18.12.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
09.12. - 10.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.12. - 03.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
26.11. - 27.11.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
24.11. - 25.11.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.11. - 27.11.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
23.11. - 23.11.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
18.11. - 19.11.2026 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.11. - 17.11.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.11. - 20.11.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
11.11. - 12.11.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.11. - 10.11.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.11. - 13.11.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
04.11. - 05.11.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.11. - 03.11.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.11. - 06.11.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
29.10. - 30.10.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
26.10. - 28.10.2026 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
21.10. - 22.10.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
19.10. - 23.10.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
15.10. - 16.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
13.10. - 14.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.10. - 16.10.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
12.10. - 13.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.10. - 09.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.10. - 09.10.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
05.10. - 06.10.2026 09:00-17:00
|
Designing an Integrated PCI Express System
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
30.09. - 01.10.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.09. - 29.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.09. - 24.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.09. - 22.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
21.09. - 23.09.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
16.09. - 17.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.09. - 18.09.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
14.09. - 15.09.2026 09:00-17:00
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x86 Foundation
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Xilinx
|
Virtual Learning Environment (Online)
|
€ 0.00
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07.09. - 08.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
07.09. - 11.09.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
02.09. - 03.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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31.08. - 04.09.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
31.08. - 01.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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27.08. - 28.08.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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26.08. - 26.08.2026 09:00-17:00
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Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
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24.08. - 25.08.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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24.08. - 28.08.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
20.08. - 21.08.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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19.08. - 21.08.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
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|
17.08. - 18.08.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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13.08. - 14.08.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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11.08. - 12.08.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
10.08. - 10.08.2026 09:00-17:00
|
UltraScale+ Spartan Compendium Live
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 0.00
|
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|
10.08. - 14.08.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
06.08. - 07.08.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
04.08. - 05.08.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
03.08. - 03.08.2026 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
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|
|
03.08. - 07.08.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
30.07. - 31.07.2026 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
27.07. - 31.07.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
27.07. - 29.07.2026 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
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|
23.07. - 24.07.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
21.07. - 22.07.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
20.07. - 24.07.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
20.07. - 21.07.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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