Table of Contents

1. INTRODUCTION

1.1 Motivation

1.2 Purpose of this tutorial

1.3 Objectives of this tutorial

1.4 One possible solution for the modulator design

1.5 Design Flow

2. FREQUENCY TRIGGER

2.1 Description

2.2 Creating a New Project

2.3 Creating Module

2.3.1 Creating a Module Using an Text Editor

2.4 Creating Test Bench

2.5 Simulating (with ISim)

3. COUNTER

3.1 Description

3.2 Creating Module

3.3 Creating Test Bench

3.4 Simulating

4. SINE PACKAGE

4.1 Description

4.2 Creating Module

5. DIGITAL SINE

5.1 Description

5.2 Creating Module

6. DIGITAL SINE tOP

6.1 Description

6.2 Creating Module

6.3 Creating Test Bench

6.4 Simulating

6.5 Synthesize

6.5.1 Description

6.5.2 Synthesize

6.5.3 Synthesis Report

6.5.4 RTL and Technology Schematic Viewers

6.5.5 View Technology Schematic

6.5.6 Check Syntax

6.5.7 Generate Post-Synthesis Simulation Model

7. PWM

7.1 Description

7.2 Creating Module

7.3 Creating Test Bench

7.4 Simulating

8. MODULATOR

8.1 Description

8.2 Creating Module

8.3 Creating Test Bench

8.4 Simulating

8.5 Creating UCF File

8.6 PlanAhead-Floorplanner

8.7 Implementation/Translation

8.7.1 Description

8.7.2 Translate

8.7.3 Translation Report

8.7.4 Generate Post-Translate Simulation Model

8.8 Implementation/Map

8.8.1 Description

8.8.2 Mapping

8.8.3 Map Report

8.8.4 Generate Post-Map Static Timing

8.8.5 Manually Place & Route (FPGA Editor)

8.8.6 Generate Post-Map Simulation Model

8.9 Implementation/Place&Route

8.9.1 Description

8.9.2 Place & Route

8.9.3 Place & Route Report

8.9.4 Generate Post-Place & Route Static Timing

8.9.5 Analyze Timing / Floorplan Design (PlanAhead)

8.9.6 View/Edit Routed Design (FPGA Editor)

8.9.7 Analyze Power Distribution (XPower Analyzer)

8.9.8 Generate Text Power Report

8.9.9 Generate Post-Place & Route Simulation Model

8.9.10 Generate IBIS Model

8.9.11 Back-annotate Pin Locations

8.10 Generate Programming File

8.10.1 Description

8.10.2 Generate Programming File Report

8.11 Configure Target Device

8.11.1 Generate Target PROM/ACE File

8.11.2 Manage Configuration Project (iMPACT)

8.12 Programming

8.13 ChipScope

8.13.1 Description

8.13.2 ChipScope Pro Cores

8.13.3 ChipScope Core Insertion

8.13.4 Analyze design using ChipScope Pro tool

8.13.5 ChipScope and VIO Core

8.14 Oscilloscope

8.15 Modifications in case of using different development boards