Vivado Design Suite for ISE Project Navigator Users

En

Course Description

This course will update experienced ISE software users to utilize the Vivado Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR,DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will learn about the scripting environment of the Vivado Design Suite and how to use the project-based scripting flow.You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast design methodology case study. The UltraFast design methodology checklist is also introduced.

Release Date

November 2018

Level

FPGA 2

Training Duration

2 days

Who Should Attend?

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use the Project Manager in the Vivado Design Suite to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation) and analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Apply HDL coding techniques and reset methodology to your design
  • Utilize a systematic approach to apply synchronous design techniques
  • Use the Vivado IP flow to add and customize IPs
  • Explain how to use Tcl commands and scripts in your design
  • Write Tcl scripts in Vivado Design Suite project and non-project modes

Course Outline

Day 1

  • Introduction to the Vivado Design Suite {Lecture}
  • Introduction to Vivado Design Flows {Lecture}
  • Vivado Design Suite Project Mode {Lecture, Lab}
  • Behavioral Simulation {Lecture}
  • Synthesis and Implementation {Lecture, Lab}
  • Basic Design Analysis in the Vivado IDE {Lab, Demo}
  • Vivado Design Suite I/O Pin Planning {Lecture, Lab}
  • Xilinx Power Estimator Spreadsheet {Lecture}
  • UltraFast Design Methodology: Board and Device Planning {Lecture, Demo}
  • HDL Coding Techniques {Lecture}
  • Resets {Lecture, Lab}
  • Register Duplication {Lecture}
  • Synchronous Design Techniques {Lecture}

Day 2

  • Vivado IP Flow {Lecture, Lab, Demo}
  • Designing with the IP Integrator {Lecture, Lab, Demo, Case Study}
  • UltraFast Design Methodology: Design Creation {Lecture}
  • Vivado Design Suite Non-Project Mode {Lecture}
  • Introduction to the Tcl Environment {Lecture, Lab}
  • Design Analysis Using Tcl Commands {Lecture, Lab, Demo}
  • Scripting in Vivado Design Suite Project Mode {Lecture, Lab}
  • Scripting in Vivado Design Suite Non-Project Mode {Lecture, Lab}

Topic Descriptions

Day 1

  • Introduction to the Vivado Design Suite – Introduces the Vivado Design Suite.
  • Introduction to Vivado Design Flows – Introduces the Vivado design flows: the project flow and non-project batch flow.
  • Vivado Design Suite Project Mode – Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
  • Behavioral Simulation – Performs behavioral simulation for your design.
  • Synthesis and Implementation – Create timing constraints according to the design scenario and synthesize and implement the design.
  • Basic Design Analysis in the Vivado IDE – Use the various design analysis features in the Vivado Design Suite.
  • Vivado Design Suite I/O Pin Planning – Use the I/O Pin Planning layout to perform pin assignments in a design.
  • Xilinx Power Estimator Spreadsheet – Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
  • UltraFast Design Methodology: Board and Device Planning – Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
  • HDL Coding Techniques – Covers basic digital coding guidelines used in an FPGA design.
  • Resets – Investigates the impact of using asynchronous resets in a design.
  • Register Duplication – Use register duplication to reduce high fanout nets in a design.
  • Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.

Day 2

  • Designing with the IP Integrator – Use the Vivado IP integrator to create the uart_led subsystem.
  • UltraFast Design Methodology: Design Creation – Overview of the methodology guidelines covered in this course.
  • Vivado Design Suite Non-Project Mode – Create a design in the
  • Vivado IP Flow – Customize IP, instantiate IP, and verify the hierarchy of your design IP.
  • Vivado Design Suite non-project mode.
  • Introduction to the Tcl Environment – Introduces Tcl (tool command language).
  • Design Analysis Using Tcl Commands – Analyze a design using Tcl commands.
  • Scripting in Vivado Design Suite Project Mode – Explains how to write Tcl commands in the project-based flow for a design.
  • Scripting in Vivado Design Suite Non-Project Mode – Write Tcl commands in the non-project batch flow for a design.

Event Schedule

No events found. Event request.

Partner

Xilinx
Updated at: 2019-07-24 11:54to the top